View ADP3189JCPZ-RLZ_2673111.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8-bit programmable 2- to 5-phase synchronous buck controller adp3189 features selectable 2-, 3-, 4-, or 5-phase operation at up to 1 mhz per phase 7.7 mv worst-case differential sensing error over temperature logic-level pwm outputs for interface to external high-power drivers active current balancing between all output phases built-in power good/crowbar bl anking supports on-the-fly vid code changes digitally programmable 0.5 v to 1.6 v output supports both vr10.x and vr11 specifications programmable short-circuit protection with programmable latch-off delay applications desktop pc power supplies for next generation intel? processors vrm modules general description the adp3189 1 is a highly efficient multi-phase synchronous buck switching regulator controller optimized for converting a 12 v main supply into the core supply voltage required by high performance intel processors. it uses an internal 8-bit dac to read a voltage identification (vid) code directly from the processor, which is used to set the output voltage between 0.5 v and 1.6 v. this device uses a multi-mode pwm architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for vr size and efficiency. the phase relation- ship of the output signals can be programmed to provide 2-, 3-, 4-, or 5-phase operation, allowing for the construction of up to five complementary buck switching stages. the adp3189 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is optimally positioned for a system transient. the adp3189 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the cpu. adp3189 is specified over the extended commercial tem- perature range of 0c to +85c and is available in a 40-lead lfcsp package. 1 protected by u.s. patent nu mber 6,683,441; others pending. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005 analog devices, inc. all rights reserved.
adp3189 rev. 0 | page 2 of 36 table of contents functional block diagram .............................................................. 3 specifications..................................................................................... 4 test circuits....................................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions ............................ 9 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 12 start-up sequence...................................................................... 12 phase detection sequence......................................................... 12 master clock frequency............................................................ 13 output voltage differential sensing ........................................ 13 output current sensing ............................................................ 13 active impedance control mode............................................. 13 current control mode and thermal balance ........................ 13 voltage control mode................................................................ 14 delay timer................................................................................. 14 soft start ...................................................................................... 14 current limit, short circuit, and latch-off protection....... 15 dynamic vid.............................................................................. 15 power good monitoring ........................................................... 15 output crowbar ......................................................................... 16 output enable and uvlo ........................................................ 16 thermal monitoring .................................................................. 16 application information................................................................ 22 setting the clock frequency ..................................................... 22 soft start delay time ................................................................. 22 current limit latch-off delay times..................................... 22 inductor selection ...................................................................... 23 designing an inductor............................................................... 23 selecting a standard inductor .............................................. 23 current sense amplifier............................................................ 24 inductor dcr temperature correction ................................. 24 load line setting........................................................................ 25 output offset .............................................................................. 26 c out selection ............................................................................. 26 power mosfets......................................................................... 27 ramp resistor selection............................................................ 28 comp pin ramp ....................................................................... 28 current limit setpoint .............................................................. 29 feedback loop compensation design.................................... 29 c in selection and input current di/dt reduction.................. 31 thermal monitor design .......................................................... 31 tuning the adp3189 ................................................................. 32 dc loadline setting .............................................................. 32 ac loadline setting............................................................... 33 initial transient setting ......................................................... 33 layout and component placement ......................................... 34 general recommendations .................................................. 34 power circuitry recommendations .................................... 34 signal circuitry recommendations .................................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 7/05revision 0: initial version
adp3189 rev. 0 | page 3 of 36 functional block diagram vcc precision reference delay uvlo shutdown and bias oscillator gnd en adp3189 18 vrhot 9 vrfan 8 t tsense 10 pwrgd 2 31 rt 13 rampadj 12 pwm2 29 14 llset 4 fb 6 ss pwm3 28 pwm4 27 pwm5 26 sw1 25 csref 15 cscomp 17 sw2 24 sw3 23 sw5 21 sw4 22 cssum 16 vid4 35 vid3 36 vid2 37 vid1 38 1 vid0 39 vid6 33 vid7 32 vid5 34 comp 5 delay 7 ilimit 11 vidsel 40 fbrtn 3 vid dac dac + 150mv dac ? 250mv csref current limit circuit crowbar current limit cmp cmp cmp cmp current balancing circuit 2-/3-/4-/5-phase driver logic enset reset reset reset reset reset pwm1 30 od 19 05626-001 850mv cmp boot voltage & soft-start control thermal throttling control + ? figure 1.
adp3189 rev. 0 | page 4 of 36 specifications vcc = 12 v, fbrtn = gnd, t a = 0c to 85c, unless otherwise noted. 1 table 1. parameter symbol conditions min typ max unit error amplifier output voltage range 2 v comp 0.95 3.95 v accuracy v fb relative to nominal dac output, referenced to fbrtn, llset = csref, figure 2 , vidsel = gnd, ?7.7 +7.7 mv vidsel = 1.25 v, vid range 1.00625 v to 1.60000 v ?7.7 +7.7 mv v fb(boot) in start-up 1.092 1.1 1.108 v load line positioning accuracy csref ? llset = 80 mv ?78 ?80 ?82 mv differential non-linearity ?1 +1 lsb line regulation v fb vcc = 10 v to 14 v 0.003 % input bias current i fb 13.5 15 16.5 a fbrtn current i fbrtn 125 200 a output current i comp fb forced to v out ? 3% 500 a gain bandwidth product gbw (err) comp = fb 20 mhz slew rate comp = fb 25 v/s llset input voltage range v llset relative to csref ?250 +250 mv llset input bias current i llset ?120 +120 na boot voltage hold time t boot c delay = 10 nf 2 ms vid inputs input low voltage v il(vid) vidx, vidsel 0.4 v input high voltage v ih(vid) vidx, vidsel 0.8 v max v ih for vid on fly 2 1.26 v input current i in(vid) ?1 a vid transition delay time 2 vid code change to fb change 200 ns no cpu detection turn-off delay time 2 vid code change to pwm going low 200 ns oscillator frequency range 2 f osc 0.25 5 mhz frequency variation f phase t a = 25c, r t = 243 k, 5-phase 180 200 220 khz t a = 25c, r t = 113 k, 5-phase 400 khz t a = 25c, r t = 51 k, 5-phase 800 khz output voltage v rt r t = 243 k to gnd 1.6 1.7 1.8 v rampadj output voltage v rampadj rampadj ? fb ?50 +50 mv rampadj input current range i rampadj 1 50 a current sense amplifier offset voltage v os(csa) cssum ? csref, figure 3 ?1.0 +1.0 mv input bias current i bias(cssum) ?50 +50 na gain bandwidth product gbw (csa) cssum = cscomp 10 mhz slew rate c cscomp = 10 pf 10 v/s input common-mode range cssum and csref 0 3 v output voltage range 0.05 2.8 v output current i cscomp 500 a current limit latch-off delay time t oc(delay) c delay = 10 nf 8 ms
adp3189 rev. 0 | page 5 of 36 parameter symbol conditions min typ max unit current balance amplifier common mode range v sw(x)cm ?600 +200 mv input resistance r sw(x) swx = 0 v 35 50 65 k input current i sw(x) swx = 0 v 2.5 4.0 5.5 a input current matching i sw(x) swx = 0 v ?5 +5 % current limit comparator output voltage v ilimit r ilimit = 143 k 1.6 1.7 1.8 v output current i ilimit r ilimit = 143 k 12 a maximum output current 2 60 a current limit threshold voltage v cl v csref ? v cscomp , r ilimit = 143 k 105 120 135 mv current limit setting ratio v cl /i ilimit 10 mv/a delay timer normal mode output current i delay 12 15 18 a output current in current limit i delay(cl) 3.0 3.75 4.5 a threshold voltage v delay(th) 1.6 1.7 1.8 v soft start output current i ss during start-up 12 15 18 a enable input threshold voltage v th(en) 800 850 900 mv hysteresis v hys(en) 80 100 120 mv input current i in(en) ?1 +1 a delay time t delay(en) en > 950 mv, c delay = 10 nf 2 ms od output output low voltage v ol( od ) 100 500 mv output high voltage v oh( od ) 4 5 v thermal throttling control ttsense voltage range internally limited 0 5.3 v ttsense vrfan threshold voltage 1.08 1.11 1.14 v ttsense vrhot threshold voltage 780 810 840 mv ttsense hysteresis 55 mv ttsense input current ?105 ?120 ?135 a vrfan output low voltage v ol(vrfan) i vrfan (sink) = ?4 ma 150 300 mv vrhot output low voltage v ol(vrhot) i vrhot (sink) = ?4 ma 150 300 mv power good comparator undervoltage threshold v pwrgd(uv) relative to nominal dac output ?200 ?250 ?300 mv overvoltage threshold v pwrgd(ov) relative to nominal dac output 100 150 200 mv output low voltage v ol(pwrgd) i pwrgd(sink) = ?4 ma 150 300 mv power good delay time during soft start 2 c delay = 10 nf 2 ms vid code changing 100 400 s vid code static 200 ns crowbar trip point v crowbar relative to nominal dac output 100 150 200 mv crowbar reset point relative to fbrtn 320 375 430 mv crowbar delay time t crowbar overvoltage to pwm going low vid code changing 100 400 s vid code static 400 ns pwm outputs output low voltage v ol(pwm) i pwm(sink) = ?400 a 160 500 mv output high voltage v oh(pwm) i pwm(source) = 400 a 4.0 5 v
adp3189 rev. 0 | page 6 of 36 parameter symbol conditions min typ max unit supply dc supply current 6 10 ma uvlo threshold voltage v uvlo vcc rising 7 7.4 7.8 v uvlo hysteresis 0.4 0.6 0.8 v 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not tested in production.
adp3189 rev. 0 | page 7 of 36 test circuits en pwrgd fbrtn fb comp ss delay vrfan vrhot ttsense pwm1 pwm2 pwm3 pwm4 pwm5 sw1 sw2 sw3 sw4 sw5 vidsel vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vcc ilimit rt rampadj llset csref cssum cscomp gnd od nc 8-bit code 10nf 1 f 10nf 100nf 12v 20k 250k 1k 100nf adp3189 40 1 1.25v + 05626-002 figure 2. closed-loop output voltage accuracy cssum 17 cscomp 16 31 vcc csref 15 gnd 18 39k 100nf 1k 1.25v adp3189 12v v os = cscomp ? 1.25v 40 05626-003 figure 3. current sense amplifier v os csref 14 llset 15 31 vcc gnd 18 adp3189 12v v 10k 1.25v 05626-004 fb 5 comp 4 vid dac + ? figure 4. positioning voltage
adp3189 rev. 0 | page 8 of 36 absolute maximum ratings table 2. parameter rating vcc ?0.3 v to +15 v fbrtn ?0.3 v to +0.3 v pwm3 to pwm5, rampadj ?0.3 v to vcc + 0.3 v sw1 to sw5 ?5 v to +25 v <200 ns ?10 v to +25 v all other inputs and outputs ?0.3 v to +5.5 v storage temperature ?65c to +150c operating ambient temperature range 0c to +85c operating junction temperature 125c thermal impedance ( ja ) 100c/w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified all other voltages re referenced to gnd. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adp3189 rev. 0 | page 9 of 36 pin configuration and function descriptions pin 1 indicator 1en 2 pwgrd 3 fbrtn 4fb 5 comp 6ss 7 delay 8 vrfan 9 vrhot 10 ttsense 27 pwm4 28 pwm3 29 pwm2 30 pwm1 26 pwm5 25 sw1 24 sw2 23 sw3 22 sw4 21 sw5 1 1 i l i m i t 1 2 r t 1 3 r a m p a d j 1 5 c s r e f 1 6 c s s u m 1 7 c s c o m p 1 8 g n d 1 9 o d 2 0 n c 1 4 l l s e t v i d 6 v i d 5 v i d 4 v i d 3 v i d 2 v i d 1 v i d 7 v c c top view (not to scale) adp3189 v i d 0 3 3 3 4 3 5 3 6 3 7 3 8 3 2 3 1 3 9 4 0 v i d s e l 05626-005 figure 5. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 en power supply enable input. pulling this pin to gnd disables the pwm outputs and pulls the pwrgd output low. 2 pwrgd power good output. open-drain output that sign als when the output voltage is outside of the proper operating range. 3 fbrtn feedback return. vid dac and error amplifier reference for remote sensing of the output voltage. 4 fb feedback input. error amplifier input for remote sens ing of the output voltage. an external resistor between this pin and the output voltage sets the no-load offset point. 5 comp error amplifier outp ut and compensation point. 6 ss soft start delay setting input. an external capacito r connected between this pin and gnd sets the soft start ramp-up time. 7 delay delay timer setting input. an external capacitor connected between this pin and gnd sets the overcurrent latch-off delay time, boot voltage hold time, en delay time, and pwrgd delay time. 8 vrfan vr fan activation output. active high open dr ain output that signals when the temperature at the monitoring point connected to ttsense exceeds the programmed vrfan temperature threshold. 9 vrhot vr hot output. active high open drain output that signals when the temperature at the monitoring point connected to ttsense exceeds the programmed vrhot temperature threshold. 10 ttsense vr hot thermal throttling sense input. an ntc thermistor between this pin and gnd is used to remotely sense the temperature at the desired thermal monitoring point. 11 ilimit current limit set point. an external resistor from this pin to gnd sets the current limit threshold of the converter. 12 rt frequency setting resistor input. an external resist or connected between this pin and gnd sets the oscillator frequency of the device. 13 rampadj pwm ramp current input. an external resistor from the converter input voltage to this pin sets the internal pwm ramp. 14 llset output load line programming input. this pin can be directly connected to cscomp, or it can be connected to the center point of a resistor divider between cs comp and csref. connecting llset to csref disables positioning. 15 csref current sense reference voltage input. the voltage on this pin is used as the reference for the current sense amplifier and the power good and crowbar functions. this pin should be connected to the common point of the output inductors. 16 cssum current sense summing node. external resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 17 cscomp current sense compensation point. a resistor and capacitor from this pin to cssum determines the gain of the current sense amplifier and the positioning loop response time. 18 gnd ground. all internal biasing and the logic output si gnals of the device are referenced to this ground. 19 od output disable logic output. this pin is actively pu lled low when the adp3189 en input is low or when vcc is below its uvlo threshold to signal to the driv er ic that the driver high -side and low-side outputs should go low. 20 nc no connect.
adp3189 rev. 0 | page 10 of 36 pin no. mnemonic description 21 to 25 sw5 to sw1 current balance inputs. inputs for measuring th e current level in each phase. the sw pins of unused phases should be left open. 26 to 30 pwm5 to pmw1 logic-level pwm outputs. each output is conne cted to the input of an external mosfet driver such as the adp3120. connecting the pwm3, pwm4, and/or pwm5 outp uts to vcc will cause that phase to turn off, allowing the adp3189 to operate as a 2-, 3-, 4-, or 5-phase controller. 31 vcc supply voltage for the device. 32 to 39 vid7 to vid0 voltage identification dac inputs. these eight pins are pulled down to gnd, providing a logic zero if left open. when in normal operation mode, the dac output programs the fb regulation voltage from 0.5 v to 1.6 v (see table 4 ). 40 vidsel vid dac selection pin. the logic state of this pin determines whether the internal vid dac decodes vid0 to vid7 as extended vr10 or vr11 inputs.
adp3189 rev. 0 | page 11 of 36 typical performance characteristics 5.0k 0 0 1000 05626-006 rt (k ) oscilator frequency (khz) 4.5k 4.0k 3.5k 3.0k 2.5k 2.0k 1.5k 1.0k 0.5k 200 500 800 figure 6. master cl ock frequency vs. rt 5.0k 0 5.8 6.6 05626-007 supply current ( a ) oscilator frequency (khz) 4.5k 4.0k 3.5k 3.0k 2.5k 2.0k 1.5k 1.0k 0.5k 6.0 6.2 6.4 figure 7. oscillator freq uency vs .supply current
adp3189 rev. 0 | page 12 of 36 theory of operation the adp3189 combines a multimode, fixed frequency pwm control with multiphase logic outputs for use in 2-, 3-, 4-, and 5-phase synchronous buck cpu core supply power converters. the internal vid dac is designed to interface with the intel 8-bit vrd/vrm 11- and 7-bit vrd/vrm 10x-compatible cpus. multiphase operation is important for producing the high currents and low voltages demanded by todays microproc- essors. handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and mosfets. the multimode control of the adp3189 ensures a stable, high performance topology for the following: ? balancing currents and thermals between phases ? high speed response at the lowest possible switching frequency and output decoupling ? minimizing thermal switching losses by using lower frequency operation ? tight load line regulation and accuracy ? high current output from having up to 5-phase operation ? reduced output ripple due to multiphase cancellation ? pc board layout noise immunity ? ease of use and design due to independent component selection ? flexibility in operation for tailoring design to low cost or high performance start-up sequence the adp3189 follows the vr11 start-up sequence shown in figure 8 . after both the en and uvlo conditions are met, the delay pin goes through one cycle (td1). after this cycle, the internal oscillator is enabled. the first five clock cycles are blanked from the pwm outputs and used for phase detection as explained in the phase detection sequence section. then, the soft start ramp is enabled (td2), and the output comes up to the boot voltage of 1.1 v. the boot hold time is determined by the delay pin as it goes through a second cycle (td3). during td3, the processor vid pins settle to the required vid code. when td3 is over, the adp3189 soft starts either up or down to the final vid voltage (td4). after td4 has been completed and the pwrgd masking time (equal to vid on the fly masking) is finished, a third ramp on the delay pin sets the pwrgd blanking (td5). vtt i/o (adp3189 en) 12v supply uvlo threshold 0.85v 1.0v delay ss vcc_core vr ready (adp3189 pwrgd ) cpu vid inputs vid invalid vid valid v delay(th) (1.7v) v boot (1.1v) v boot (1.1v) v vid v vid td1 td2 td4 td5 50 s td3 05626-008 figure 8. system start-up sequence phase detection sequence during start-up, the number of operational phases and their phase relationship is determined by the internal circuitry moni- toring the pwm outputs. normally, the adp3189 operates as a 5-phase pwm controller. connecting the pwm5 pin to vcc programs a 4-phase operation, and connecting the pwm5 pin and pwm4 pin to vcc programs a 3-phase operation. for 2-phase operation, connect pwm5, pwm4, and pwm3 to vcc. prior to soft start, while en is low, the pwm3, pwm4, and pwm5 pins sink approximately 100 a. an internal compara- tor checks each pins voltage vs. a threshold of 3.15 v. if the pin is tied to vcc, it is above the threshold. otherwise, an internal current sink pulls the pin to gnd, which is below the threshold. pwm1 and pwm2 are low during the phase detection interval, which occurs during the first five clock cycles of the internal oscillator. after this time, if the remaining pwm outputs are not pulled to vcc, the 100 a current sink is removed, and they function as normal pwm outputs. if they are pulled to vcc, the 100 a current source is removed, and the outputs are put into a high-impedance state. the pwm outputs are logic-level devices intended for driving external gate drivers such as the adp3120. since each phase is monitored independently, operation approaching 100% duty cycle is possible. also, more than one output can be on at the same time to allow overlapping phases.
adp3189 rev. 0 | page 13 of 36 master clock frequency the clock frequency of the adp3189 is set with an external resistor connected from the rt pin to ground. the frequency follows the graph in figure 6 . to determine the frequency per phase, the clock is divided by the number of phases in use. if all phases are in use, divide by 5. if pwm5 is tied to vcc, then divide the master clock by 4 for the frequency of the remaining phases. if pwm4 and pwm5 are tied to vcc, then divide by 3. if pwm3, pwm4, and pwm5 are tied to vcc, then divide by 2. output voltage differential sensing the adp3189 combines differential sensing with a high accuracy vid dac and reference and a low offset error ampli- fier. this maintains a worst-case specification of 7.7 mv differential sensing error over its full operating output voltage and temperature range. the output voltage is sensed between the fb pin and fbrtn pin. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 125 a to allow accurate remote sensing. the internal error amplifier compares the output of the dac to the fb pin to regulate the output voltage. output current sensing the adp3189 provides a dedicated current-sense amplifier (csa) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side mosfet. this amplifier can be configured several ways, depending on the objectives of the system, as follows: ? output inductor dcr sensing without a thermistor for lowest cost. ? output inductor dcr sensing with a thermistor for improved accuracy with tracking of inductor temperature. ? sense resistors for highest accuracy measurements. the positive input of the csa is connected to the csref pin, which is connected to the output voltage. the inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input, cssum. the feedback resistor between cscomp and cssum sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. the gain of the amplifier is programmable by adjusting the feedback resistor. an additional resistor divider connected between csref and cscomp, with the mid point connected to llset, can be used to set the load line required by the microprocessor. the current information is then given as csref C llset. this difference signal is used internally to offset the vid dac for voltage positioning. the difference between csref and cscomp is then used as a differential input for the current-limit comparator. this allows for the load line to be set independ- ently of the current-limit threshold. in the event that the current limit threshold and load line are not independent, the resistor divider between csref and cscomp can be removed and the cscomp pin can be directly connected to llset. to disable voltage positioning entirely (that is, no load line) connect llset to csref. to provide the best accuracy for sensing current, the csa is designed to have a low offset input voltage. also, the sensing gain is determined by external resistors, so that it can be made extremely accurate. active impedance control mode for controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the llset pin can be scaled to be equal to the droop imped- ance of the regulator times the output current. this droop voltage is then used to set the input control voltage to the system. the droop voltage is subtracted from the dac reference input voltage directly to tell the error amplifier where the output voltage should be. this allows enhanced feed-forward response. current control mode and thermal balance the adp3189 has individual inputs (sw1 to sw5) for each phase, which are used for monitoring the current of each phase. this information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. this current balance information is independent of the average output current information used for positioning as described in the output current sensing section. the magnitude of the internal ramp can be set to optimize the transient response of the system. it also monitors the supply volt- age for feed-forward control for changes in the supply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. external resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase has better cooling and can support higher currents. resistors r sw1 through r sw5 (see the typical application circuit in figure 11 ) can be used for adjusting thermal balance. it is best to have the ability to add these resistors during the initial design, so ensure that placeholders are provided in the layout.
adp3189 rev. 0 | page 14 of 36 to increase the current in any given phase, enlarge r sw for that phase (make r sw = 0 for the hottest phase and do not change during balancing). increasing r sw to only 500 makes a substantial increase in phase current. increase each r sw value by small amounts to achieve balance, starting with the coolest phase first. voltage control mode a high gain-bandwidth voltage mode error amplifier is used for the voltage-mode control loop. the control input voltage to the positive input is set via the vid logic according to the voltages listed in table 4 . this voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with a resistor r b and is used for sensing and controlling the output voltage at this point. a current source from the fb pin flowing through r b is used for setting the no-load offset voltage from the vid voltage. the no-load voltage is negative with respect to the vid dac. the main loop compensation is incorporated into the feedback network between fb and comp. delay timer the delay times for the start-up timing sequence are set with a capacitor from the delay pin to ground. in uvlo, or when en is logic low, the delay pin is held at ground. after the uvlo and en signals are asserted, the first delay time (td1 in figure 8 ) is initiated. a 15 a current flows out of the delay pin to charge c dly . a comparator monitors the delay voltage with a threshold of 1.7 v. the delay time is therefore set by the 15 a charging a capacitor from 0 v to 1.7 v. this delay pin is used for multiple delay timings (td1, td3, and td5) during the start-up sequence. also, delay is used for timing the current limit latch off, as explained in the current limit, short circuit, and latch-off protection section. soft start the soft start times for the output voltage are set with a capacitor from the ss pin to ground. after td1 and the phase detection cycle have been completed, the ss time (td2 in figure 8 ) starts. the ss pin is disconnected from gnd, and the capacitor is charged up to the 1.1 v boot voltage by the ss amplifier, which has a limited output current of 15 a. the voltage at the fb pin follows the ramping voltage on the ss pin, limiting the inrush current during start-up. the soft start time depends on the value of the boot voltage and c ss . once the ss voltage is within 100 mv of the boot voltage, the boot voltage delay time (td3) is started. the end of the boot voltage delay time signals the beginning of the second soft start time (td4). the ss voltage now changes from the boot voltage to the programmed vid dac voltage (either higher or lower) using the ss amplifier with the limited output current of 15 a. the voltage of the fb pin follows the ramping voltage of the ss pin, limiting the inrush current during the transition from the boot voltage to the final dac voltage. the second soft start time depends on the boot voltage, the programmed vid dac voltage, and c ss . if either en is taken low or vcc drops below uvlo, delay and ss are reset to ground to be ready for another soft start cycle. figure 9 shows typical start-up waveforms for the adp3189. 05626-009 ch1 1.0v ch2 1.0v ch3 1.0v ch4 10.0v m2.00ms a ch1 500v 1 3 2 4 t 22.0% figure 9. typical start-up waveforms channel 1: csref, channel 2: delay, channel 3: ss, channel 4: phase 1 switch node
adp3189 rev. 0 | page 15 of 36 current limit, short circuit, and latch-off protection the adp3189 compares a programmable current-limit set point to the voltage from the output of the current-sense amplifier. the level of current limit is set with the resistor from the ilimit pin to ground. during operation, the voltage on ilimit is 1.7 v. the current through the external resistor is internally scaled to give a current limit threshold of 10 mv/a. if the difference in voltage between csref and cscomp rises above the current limit threshold, the internal current limit amplifier controls the internal comp voltage to maintain the average output current at the limit. if the limit is reached and td5 has completed, a latch-off delay time starts, and the controller shuts down if the fault is not removed. the current limit delay time shares the delay pin timing capacitor with the start-up sequence timing. however, during current limit, the delay pin current is reduced to 3.75 a. a comparator monitors the delay voltage and shuts off the controller when the voltage reaches 1.7 v. therefore, the current limit latch-off delay time is set by the current of 3.75 a, charging the delay capacitor from 0 v to 1.7 v. this delay is four times longer than the delay time during the start- up sequence. the current limit delay time starts only after the td5 has completed. if there is a current limit during start-up, the adp3189 goes through td1 to td5, and then starts the latch- off time. because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.7 v threshold is reached, the controller returns to normal operation, and the delay capacitor is reset to gnd. the latch-off function can be reset by either removing and reapplying the supply voltage to the adp3189, or by toggling the en pin low for a short time. to disable the short circuit latch-off function, an external resistor should be placed in parallel with c dly . this prevents the delay capacitor from charging up to the 1.7 v threshold. the addition of this resistor will cause a slight increase in the delay times. during start-up, when the output voltage is below 200 mv, a secondary current limit is active. this is necessary because the voltage swing of cscomp cannot go below ground. this secondary current limit controls the internal comp voltage to the pwm comparators to 1.5 v. this limits the voltage drop across the low-side mosfets through the current balance circuitry. an inherent per-phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. this limit is based on the maximum normal mode comp voltage. typical overcurrent latch-off waveforms are shown in figure 10 . 05626-010 ch1 1.0v ch2 1.0v ch3 1.0v ch4 10.0v m2.00ms a ch1 500v 1 3 2 4 t 22.0% figure 10. overcurrent latch-off waveforms channel 1: csref, channel 2: delay, channel 3: comp, channel 4: phase 1 switch node dynamic vid the adp3189 has the ability to dynamically change the vid inputs while the controller is running. this allows the output voltage to change while the supply is running and supplying current to the load. this is commonly referred to as vid on- the-fly (otf). a vid otf can occur under light or heavy load conditions. the processor signals the controller by changing the vid inputs in multiple steps from the start code to the finish code. this change can be positive or negative. when a vid input changes state, the adp3189 detects the change and ignores the dac inputs for a minimum of 200 ns. this time prevents a false code due to logic skew while the eight vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar blanking functions for a minimum of 100 s to prevent a false pwrgd or crowbar event. each vid change resets the internal timer. power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the nominal limits specified based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range, if the vid dac inputs are in no cpu mode, or whenever the en pin is pulled low. pwrgd is blanked during a vid otf event for a period of 400 s to prevent false signals during the time the output is changing.
adp3189 rev. 0 | page 16 of 36 the pwrgd circuitry also incorporates an initial turn-on delay time (td5), based on the delay timer. prior to the ss voltage reaching the programmed vid dac voltage and the pwrgd masking time finishing, the pwrgd pin is held low. once the ss pin is within 100 mv of the programmed dac voltage, the capacitor on the delay pin begins to charge up. a comparator monitors the delay voltage and enables pwrgd when the voltage reaches 1.7 v. the pwrgd delay time is, therefore, set by a current of 15 a, charging a capacitor from 0 v to 1.7 v. output crowbar as part of the protection for the load and output components of the supply, the pwm outputs are driven low, turning on the low-side mosfets, when the output voltage exceeds the upper crowbar threshold. this crowbar action stops once the output voltage falls below the release threshold of approximately 375 mv. turning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvoltage is due to a short in the high-side mosfet, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. output enable and uvlo for the adp3189 to begin switching, the input supply (vcc) to the controller must be higher than the uvlo threshold, and the en pin must be higher than its 0.85 v threshold. this initiates a system start up sequence. if either uvlo or en is less than their respective thresholds, the adp3189 is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and forces pwrgd and od signals low. in the application circuit, the od pin should be connected to the od inputs of the adp3120 driver. grounding od disables the drivers such that both drvh and drvl are grounded. this feature is important in preventing the discharge of the output capacitors when the controller is shut off. if the driver outputs were not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. thermal monitoring the adp3189 includes a thermal monitoring circuit to detect when a point on the vr has exceeded two different user-defined temperatures. the thermal monitoring circuit requires an ntc thermistor to be placed between ttsense and gnd. a fixed current of 120 a is sourced out of the ttsense pin and into the thermistor. the current source is internally limited to 5 v. an internal circuit compares the ttsense voltage to a 1.11 v and a 0.81 v threshold, and outputs an open-drain signal at the vrfan and vrhot outputs, respectively. once the voltage on the ttsense pin goes below its respective threshold, the open drain outputs assert high to signal the system that an overtem- perature event has occurred. since the ttsense voltage changes slowly with respect to time, 55 mv of hysteresis is built into these comparators. the thermal monitoring circuitry does not depend on en and is active when uvlo is above its threshold. when uvlo is below its threshold, vrfan and vrhot are forced low.
adp3189 rev. 0 | page 17 of 36 table 4.vr11 and vr10.x vid codes for the adp3189 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 off 0 0 0 0 0 0 0 0 n/a off 0 0 0 0 0 0 0 1 n/a 1.60000 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1.59375 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1.58750 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1.58125 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1.57500 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1.56875 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 1.56250 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1.55625 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1.55000 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 1.54375 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1.53750 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1.53125 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 1.52500 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 1.51875 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 1.51250 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1.50625 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1.50000 0 0 0 1 0 0 1 0 0 1 1 1 0 1 1 1.49375 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1.48750 0 0 0 1 0 1 0 0 0 1 1 1 1 0 1 1.48125 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1.47500 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1.46875 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1.46250 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1.45625 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1.45000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1.44375 0 0 0 1 1 0 1 1 1 0 0 0 0 1 0 1.43750 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1.43125 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 1.42500 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1.41875 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 1.41250 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1.40625 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1.40000 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1.39375 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 1.38750 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1.38125 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1.37500 0 0 1 0 0 1 1 0 1 0 0 1 1 1 1 1.36875 0 0 1 0 0 1 1 1 1 0 0 1 1 1 0 1.36250 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 1.35625 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 1.35000 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1.34375 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1.33750 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 1.33125 0 0 1 0 1 1 0 1 1 0 1 0 1 0 0 1.32500 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1.31875 0 0 1 0 1 1 1 1 1 0 1 0 1 1 0
adp3189 rev. 0 | page 18 of 36 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 1.31250 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1.30625 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1.30000 0 0 1 1 0 0 1 0 1 0 1 1 0 1 1 1.29375 0 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1.28750 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1.28125 0 0 1 1 0 1 0 1 1 0 1 1 1 0 0 1.27500 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1.26875 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1.26250 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1.25625 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1.25000 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 1.24375 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 1.23750 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1.23125 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 1.22500 0 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1.21875 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1.21250 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 1.20625 0 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1.20000 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1.19375 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1.18750 0 1 0 0 0 1 0 0 1 1 0 1 1 0 1 1.18125 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 1.17500 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1.16875 0 1 0 0 0 1 1 1 1 1 0 1 1 1 0 1.16250 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1.15625 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1.15000 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1.14375 0 1 0 0 1 0 1 1 1 1 1 0 0 1 0 1.13750 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1.13125 0 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1.12500 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1.11875 0 1 0 0 1 1 1 1 1 1 1 0 1 1 0 1.11250 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1.10625 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1.10000 0 1 0 1 0 0 1 0 1 1 1 1 0 1 1 1.09375 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0 off n/a 1 1 1 1 1 0 1 off n/a 1 1 1 1 1 0 0 off n/a 1 1 1 1 1 1 1 off n/a 1 1 1 1 1 1 0 1.08750 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1.08125 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1.07500 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1.06875 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1.06250 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1 1.05625 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 1.05000 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1.04375 0 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1.03750 0 1 0 1 1 1 0 0 0 0 0 1 0 0 1
adp3189 rev. 0 | page 19 of 36 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 1.03125 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 1.02500 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1.01875 0 1 0 1 1 1 1 1 0 0 0 1 0 1 0 1.01250 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1.00625 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1.00000 0 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0.99375 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0.98750 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0.98125 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0.97500 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0.96875 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0.96250 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0.95625 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 0.95000 0 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0.94375 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0.93750 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0.93125 0 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0.92500 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0.91875 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 0.91250 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 0.90625 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0.90000 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0.89375 0 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0.88750 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0.88125 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0.87500 0 1 1 1 0 1 1 0 0 1 0 0 0 1 1 0.86875 0 1 1 1 0 1 1 1 0 1 0 0 0 1 0 0.86250 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0.85625 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 0.85000 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1 0.84375 0 1 1 1 1 0 1 1 0 1 0 0 1 1 0 0.83750 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0.83125 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0.82500 0 1 1 1 1 1 1 0 n/a 0.81875 0 1 1 1 1 1 1 1 n/a 0.81250 1 0 0 0 0 0 0 0 n/a 0.80625 1 0 0 0 0 0 0 1 n/a 0.80000 1 0 0 0 0 0 1 0 n/a 0.79375 1 0 0 0 0 0 1 1 n/a 0.78750 1 0 0 0 0 1 0 0 n/a 0.78125 1 0 0 0 0 1 0 1 n/a 0.77500 1 0 0 0 0 1 1 0 n/a 0.76875 1 0 0 0 0 1 1 1 n/a 0.76250 1 0 0 0 1 0 0 0 n/a 0.75625 1 0 0 0 1 0 0 1 n/a 0.75000 1 0 0 0 1 0 1 0 n/a 0.74375 1 0 0 0 1 0 1 1 n/a 0.73750 1 0 0 0 1 1 0 0 n/a 0.73125 1 0 0 0 1 1 0 1 n/a
adp3189 rev. 0 | page 20 of 36 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 0.72500 1 0 0 0 1 1 1 0 n/a 0.71875 1 0 0 0 1 1 1 1 n/a 0.71250 1 0 0 1 0 0 0 0 n/a 0.70625 1 0 0 1 0 0 0 1 n/a 0.70000 1 0 0 1 0 0 1 0 n/a 0.69375 1 0 0 1 0 0 1 1 n/a 0.68750 1 0 0 1 0 1 0 0 n/a 0.68125 1 0 0 1 0 1 0 1 n/a 0.67500 1 0 0 1 0 1 1 0 n/a 0.66875 1 0 0 1 0 1 1 1 n/a 0.66250 1 0 0 1 1 0 0 0 n/a 0.65625 1 0 0 1 1 0 0 1 n/a 0.65000 1 0 0 1 1 0 1 0 n/a 0.64375 1 0 0 1 1 0 1 1 n/a 0.63750 1 0 0 1 1 1 0 0 n/a 0.63125 1 0 0 1 1 1 0 1 n/a 0.62500 1 0 0 1 1 1 1 0 n/a 0.61875 1 0 0 1 1 1 1 1 n/a 0.61250 1 0 1 0 0 0 0 0 n/a 0.60625 1 0 1 0 0 0 0 1 n/a 0.60000 1 0 1 0 0 0 1 0 n/a 0.59375 1 0 1 0 0 0 1 1 n/a 0.58750 1 0 1 0 0 1 0 0 n/a 0.58125 1 0 1 0 0 1 0 1 n/a 0.57500 1 0 1 0 0 1 1 0 n/a 0.56875 1 0 1 0 0 1 1 1 n/a 0.56250 1 0 1 0 1 0 0 0 n/a 0.55625 1 0 1 0 1 0 0 1 n/a 0.55000 1 0 1 0 1 0 1 0 n/a 0.54375 1 0 1 0 1 0 1 1 n/a 0.53750 1 0 1 0 1 1 0 0 n/a 0.53125 1 0 1 0 1 1 0 1 n/a 0.52500 1 0 1 0 1 1 1 0 n/a 0.51875 1 0 1 0 1 1 1 1 n/a 0.51250 1 0 1 1 0 0 0 0 n/a 0.50625 1 0 1 1 0 0 0 1 n/a 0.50000 1 0 1 1 0 0 1 0 n/a off 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
adp3189 rev. 0 | page 21 of 36 * for a description of optional r sw resistors, see the theory of operation section 1 2 3 8 7 6 4 5 bst in od vc c drvh sw pgnd drvl u1 adp3189 from cpu 1 2 3 8 7 6 4 5 bst in od vc c drvh sw pgnd drvl u5 adp3120 u4 adp3120 u3 adp3120 1 2 3 8 7 6 4 5 bst in od vc c drvh sw pgnd drvl pwm1 pwm2 pwm3 pwm4 pwm5 sw1 sw2 sw3 sw4 sw5 vidsel vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vcc ilimit rt rampadj llset csref cssum cscomp gnd od nc en pwrgd fbrtn fb comp ss delay vr f an vr hot tts ens e 1 40 ** conne ct near e ach induc tor r3 1 c8 1nf c b 560pf r b 1.00k rth1 100k , 5% ntc r lim 100k 1% r cs2 88.7k r cs1 35.7k r ph3 158k 1% r ph4 158k 1% r ph2 158k 1% r ph1 158k 1% r sw4 * r sw3 * r sw2 * r sw1 * r t 182k 1% r a 10.0k c fb 27pf c dly 18nf c ss 39nf c3 100 f (c3 optional) c4 1 f r1 10 d1 1n4148 v in 12v v in rtn c1 c2 c6 0.1 f c7 1nf c cs1 1nf 5% npo c cs2 1nf 5% npo c22 4.7 f c18 4.7 f c5 1nf c a 560nf power good vtt i/o vrfan prochot r7 2.2 l1 370nh 18a 2700 f / 16v / 3.3 a2 sanyo mv-wx series ++ c14 4.7 f d5 1n4148 d4 1n4148 d3 1n4148 c21 18nf r6 2.2 c17 18nf r5 2.2 c13 18nf q13 ntd40n03 q9 ntd40n03 q11 ntd110n02 q12 ntd110n02 q14 ntd40n03 q15 ntd110n02 q16 ntd110n02 c23 10nf c24 4.7 f c19 10nf c15 10nf q10 ntd40n03 c20 4.7 f l5 320nh/1.4m l4 320nh/1.4m q5 ntd40n03 q7 ntd110n02 q8 ntd110n02 q6 ntd40n03 c16 4.7 f l3 320nh/1.4m 1 2 3 8 7 6 4 5 bst in od vc c drvh sw pgnd drvl u2 adp3120 c10 4.7 f d2 1n4148 r4 2.2 c9 18nf c25 c34 c11 10nf q1 ntd40n03 q3 ntd110n02 q4 ntd110n02 560 f / 4v / 4v10 sanyo sepc series 5m each q2 ntd40n03 c12 4.7 f l2 320nh/1.4m rth2 100k , 5% ntc 10 ** 10 ** 10 ** 1 0 * * ++ v cc(core) 0.5v?1.6v 115a tdc, 130a pk v cc(sense) v ss(sense) v cc(core) rtn 10 f18 mlcc in socket 05626-011 figure 11.typical 4-phase application circuit
adp3189 rev. 0 | page 22 of 36 application information the design parameters for a typical intel vrd 11 compliant cpu application are as follows: ? input voltage (v in ) = 12 v ? vid setting voltage (v vid ) = 1.300 v ? duty cycle (d) = 0.108 ? nominal output voltage at no load (v onl ) = 1.285 v ? nominal output voltage at 115 a load (v ofl ) = 1.170 v ? static output voltage drop based on a 1.0 m load line (r o ) from no load to full load (v d ) = v onl ? v ofl = 1.285 v ? 1.170 v = 115 mv ? maximum output current (i o ) = 130 a ? maximum output current step (i o ) = 100 a ? maximum output current slew-rate (s r ) = 200 a/ sec ? number of phases (n) = 4 ? switching frequency per phase (f sw ) = 330 khz setting the clock frequency the adp3189 uses a fixed-frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors, and of the input and output capacitors. with n = 4 for four phases, a clock frequency of 1.32 mhz sets the switching frequency (f sw ) of each phase to 330 khz, which represents a practical trade-off between the switching losses and the sizes of the out- put filter components. equation 1 shows that to achieve a 1.32 mhz oscillator frequency, the correct value for r t is 181 k. alternatively, the value for r t can be calculated using ? = k13 pf9.3 1 sw t fn r (1) where 3.9 pf and 13 k are internal ic component values. for good initial accuracy and frequency stability, a 1% resistor is recommended. soft start delay time the value of c ss sets the soft start time. the ramp is generated with a 15 a internal current source. the value for c ss can be found using: boot ss v td c 2 a15 = (2) where td2 is the desired soft start time and v boot is internally set to 1.1 v. assuming a desired td2 time of 3 ms, c ss is 41 nf. the closest standard value for c ss is 39 nf. although c ss also controls the time delay for td4 (which is determined by the final vid voltage), the minimum specification for td4 is 0 ns. this means that as long as the td2 time requirement is met, td4 will be within the specification. current limit latc h-off delay times the start-up and current limit delay times are determined by the capacitor connected to the delay pin. the first step is to set c dly for the td1, td3, and td5 delay times (see figure 8 ). the delay ramp ( i delay ) is generated using a 15 a internal current source. the value for c dly can be approximated using: )( )( thdelay delay dly v xtd ic = (3) where td(x) is the desired delay time for td1, td3, and td5. the delay threshold voltage ( v delay(th) ) is given as 1.7 v. in this example, 2 ms is chosen for all three delay times, which meets intels specification. solving for c dly gives a value of 17.6 nf. the closest standard value for c dly is 18 nf. when the adp3189 goes into current limit, the internal current source changes from 15 a to 3.75 a. this makes the latch-off delay time 4 times longer than the start-up delay time. longer latch-off delay times can be achieved by placing a resistor in parallel with c dly .
adp3189 rev. 0 | page 23 of 36 inductor selection the choice of inductance for the inductor determines the ripple current in the inductor. less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the mosfets, but allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger inductors and more output capacitance for the same peak-to-peak transient deviation. in any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. () lf d v i sw vid r ? = 1 (4) () () ripple sw o vid vf dnrv l ? 1 (5) solving equation 5 for an 8 mv p-p output ripple voltage yields () nh802 mv8khz330 0.4321 m 1.0v1.3 = ? l if the resulting ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. this allows optimal transient response and minimum output decoupling. the smallest possible inductor should be used to minimize the number of output capacitors. for this example, choosing a 320 nh inductor is a good starting point and gives a calculated ripple current of 11 a. the inductor should not saturate at the peak current of 35.5 a and should be able to handle the sum of the power dissipation caused by the average current of 30 a in the winding and core loss. another important factor in the inductor design is the dcr (r l ), which is used for measuring the phase currents. a large dcr can cause excessive power losses, while too small a value can lead to increased measurement error. a good rule is to have the dcr be about 1 to 1? times the droop resistance (r o ). this example uses an inductor with a dcr of 1.4 m. designing an inductor once the inductance and dcr are known, the next step is to either design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. it is also important to have the inductance and dcr tolerance specified to control the accuracy of the system. 15% inductance and 7% dcr, at room temperature, are reasonable tolerances most manufacturers can meet. the first decision in designing the inductor is choosing the core material. several possibilities for providing low core loss at high frequencies include the powder cores (for example, kool-m? from magnetics, inc. or from micrometals) and the gapped soft ferrite cores (for example, 3f3 or 3f4 from philips). low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. the best choice for a core geometry is a closed-loop type such as a potentiometer core; pq, u, or e core; or toroid. a good compromise between price and performance is a core with a toroidal shape. many useful magnetics design references are available for quickly designing a power inductor, such as ? magnetic designer software intusoft (www.intusoft.com) ? designing magnetic components for high-frequency dc- dcconverters , by william t. mclyman, kg magnetics, inc., isbn 1883107008 selecting a standard inductor the following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. ? coilcraft www.coilcraft.com ? coiltronics www.coiltronics.com ? sumida electric company www.sumida.com ? vishay intertechnology www.vishay.com
adp3189 rev. 0 | page 24 of 36 current sense amplifier most designs require the regulator output voltage, measured at the cpu pins, to drop when the output current increases. the specified voltage drop corresponds to a dc output resistance (r o ), also referred to as a load line. the adp3189 has the flexibility of adjusting r o , independent of current limit or compensation components, and it can also support cpus that do not require a load line. for designs requiring a load line, the impedance gain of the cs amplifier (r csa ) must be to be greater than or equal to the load line. all designs, whether they have a load line or not, should keep r csa 1 m. the output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. this summer filter is the cs amplifier configured with resistors r ph(x) (summers), and r cs and c cs (filter). the impedance gain of the regulator is set by the following equations, where r l is the dcr of the output inductors: () l xph cs csa r r r r = (6) cs l cs rr l c = (7) the user has the flexibility of choosing either r cs or r ph(x) . however, it is best to select r cs equal to 100 k, and then solve for r ph(x) by rearranging equation 6. here r csa = r o = 1 m since this is equal to our design loadline. () () k140k100 m 0.1 m4.1 == = xph cs csa l x ph r r r r r next, use equation 7 to solve for c cs . nf82.2 k100m4.1 nh320 = = cs c it is best to have a dual location for c cs in the layout so that standard values can be used in parallel to get as close to the value desired. for best accuracy, c cs should be a 5% or 10% npo capacitor. this example uses a 5% combination for c cs of two 1 nf capacitors in parallel. recalculating r cs and r ph(x) using this capacitor combination yields 114 k and 160 k. the closest standard 1% value for r ph(x) is 158 k. inductor dcr temperature correction with the inductors dcr is used as the sense element and copper wire is the source of the dcr, the user needs to compensate for temperature changes of the inductors winding. fortunately, copper has a well known temperature coefficient (tc) of 0.39%/c. if r cs is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the tempera- ture variation of the inductors dcr. due to the nonlinear nature of ntc thermistors, resistors r cs1 and r cs2 are needed. see figure 12 to linearize the ntc and produce the desired temperature tracking. csref cssum cscomp 17 16 18 c cs1 c cs2 r cs1 r cs2 r ph1 r tm r ph2 r ph3 place as close as possible to the nearest inductor keep this path as short as possible and well away from switch node lines adp3189 05626-012 figure 12. temperature compensation circuit values the following procedure and expressions yield values to use for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value. 1. select an ntc based on type and value. since the value is unknown, use a thermistor with a value close to r cs . the ntc should also have an initial tolerance of better than 5%. 2. based on the type of ntc, find its relative resistance value at two temperatures. the temperatures that work well are 50c and 90c. these resistance values are called a (r th(50c) )/r th(25c) ) and b (r th(90c) )/r th(25c) ). the ntcs relative value is always 1 at 25c. 3. find the relative value of r cs required for each of these temperatures. this is based on the percentage change needed, which in this example is initially 0.39%/c. these are called r 1 (1/(1 + tc ( t 1 ? 25))) and r 2 (1/(1 + t c ( t 2 ? 25))), where tc = 0.0039 for copper. t 1 = 50c and t 2 = 90c are chosen. from this, calculate that r 1 = 0.9112 and r 2 = 0.7978.
adp3189 rev. 0 | page 25 of 36 1. compute the relative values for r cs1 , r cs2 , and r th using ( ) () () () () ( ) barabrba rabrbarrba r 2 1 1 2 21 cs2 ????? ?+??? = (8) () cs21cs2 cs1 rr a r a r ? ? ? ? = (9) cs1 cs2 th rr r 1 1 1 1 ? ? = (10) calculate r th = r th r cs , then select the closest value of thermistor available. also, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: () () calculated th actual th r r k = (11) 2. calculate values for r cs1 and r cs2 using equation 12 and equation 13: cs1 cs cs1 rkrr = (12) ( ) ( ) ( ) cs2 cs cs2 rkkrr +?= (13) in this example, r cs was calculated to be 114 k. look for an available 100 k thermistor, 0603 size. one such thermistor is the vishay nths0603n01n1003jr ntc thermistor with a = 0.3602 and b = 0.09174. from these values, compute r cs1 = 0.3795, r cs2 = 0.7195, and r th = 1.075. solving for r th yields 122.55 k, so 100 k is chosen, making k = 0.816. next find r cs1 and r cs2 to be 35.3 k and 87.9 k. finally, choose the closest 1% resistor values, which yields a choice of 35.7 k and 88.7 k. load line setting for load line values greater than 1 m, r csa can be set equal to r o , and the llset pin can be directly connected to the cscomp pin. when the load line value needs to be less than 1 m, two additional resistors are required. figure 13 shows the placement of these resistors. csref llset cssum cscomp 16 15 17 adp3189 05626-013 14 r ll1 r ll2 q ll optional load line select switch figure 13. load line setting resistors the two resistors r ll1 and r ll2 set up a divider between the cscomp pin and csref pin. this resistor divider is input into the llset pin to set the load line slope r o of the vr according to the following equation: csa ll ll ll o r rr r r + = (14) for best results, start with a 1% resistor of 20.0 k for r ll2 . then, solve for the required value of r ll1 by rearranging equation 14 as follows: csa ll ll ll o r rr r r + = another useful feature for some vr applications is the ability to select different load lines. figure 13 shows an optional mosfet switch that allows this. here, design for r csa = r o(max) (selected with q ll on) and then use equation 14 to set r o = r o(min) (selected with q ll off). for this design, r csa = r o = 1 m, so connect llset directly to cscomp, and the resistors r ll1 and r ll2 are not needed.
adp3189 rev. 0 | page 26 of 36 output offset the intel specification requires that at no load the nominal output voltage of the regulator is offset to a value lower than the nominal voltage corresponding to the vid code. the offset is set by a constant current source flowing out of the fb pin (i fb ) and flowing through r b . the value of r b can be found using equation 15: fb onl vid b i v v r ? = k00.1 a15 v285.1v3.1 = ? = b r (15) the closest standard 1% resistor value is 1.00 k. c out selection the required output decoupling for the regulator is typically recommended by intel for various processors and platforms. use some simple design guidelines to determine the require- ments. these guidelines are based on having both bulk capacitors and ceramic capacitors in the system. first, select the total amount of ceramic capacitance. this is based on the number and type of capacitor to be used. the best location for ceramic capacitors is inside the socket, with 12 to 18 of size, 1206 being the physical limit. other capacitors can be placed along the outer edge of the socket as well. to aid in determining the minimum amount of ceramic capacitance required, start with a worst-case load step occur- ring right after a switching cycle has stopped. the ceramic capacitance then delivers the charge to the load while the load is ramping up and until the vr has responded with the next switching cycle. the following equation gives the designer a rough approximation for determining the minimum ceramic capacitance needed. due to the complexity of the pcb parasitics and bulk capacitors, the actual amount of ceramic capacitance required may vary. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? r o sw o minz s i d nfr c 2 111 (16) the typical ceramic capacitors used are made up of multiple 10 f or 22 f capacitors. for this example, equation 16 yields 180.8 f, so eighteen 10 uf ceramics will suffice. next, there is an upper limit imposed on the total amount of bulk capacitance (c x ) when the user considers the vid on-the- fly voltage stepping of the output (voltage step v a lower limit is based on meeting the capacitance for load release for a given maximum load step i o and a maximum allowable overshoot. the total amount of load release voltage is given as v o = i o r o + v rl , where v rl is the maximum allowable overshoot voltage. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + z vid o rl o o min x c v i v rn il c (17) () maxx c (18) z o v vid v vid v 2 o 2 c l nkr v v t v v rnk l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 ? ? ? ? ? ? ? ? ?= v err v v 1nk where to meet the conditions of these expressions and transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance (r o ). if the c x(min) is larger than c x(max) , the system cannot meet the vid on-the-fly speci- fication and can require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). this example uses eighteen 10 f 1206 mlc capacitors ( c z = 180 f). the vid on-the-fly step change is 450 mv in 230 s with a setting error of 2.5 mv. the maximum allowable load release overshoot for this example is 50 mv, therefore solving for the bulk capacitance yields () mf92.3f180 v3.1 a100 mv50 m 0.14 a100nh320 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + minx c () () v3.1m0.12.54 mv450nh320 2 2 maxx c mf043 f1801 nh320mv450 m0125431s230 1 2 . ..v. = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + v in time t v with error of v err ). where k = 5.2
adp3189 rev. 0 | page 27 of 36 using ten 560 f al-poly capacitors with a typical esr of 6 m each yields c x = 5.6 mf with an r x = 0.6 m. one last check should be made to ensure that the esl of the bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using () ph024 3 4 m 1f180 2 = x 2 2 o zx l qrcl (19) where q 2 is limited to 4 / 3 to ensure a critically damped system. in this example, l x is approximately 240 ph for the ten a1-polys capacitors, which satisfies this limitation. if the l x of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased, or lower esl bulks used if there is excessive undershoot during a load transient. for this multimode control tech nique, all ceramic designs can be used providing the conditions of equation 16, equation 17, equation 18, and equation 19 are satisfied. power mosfets for this example, the n-channel power mosfets have been selected for one high-side switch and two low-side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . the minimum gate drive voltage (the supply voltage to the adp3120) dictates whether standard threshold or logic-level threshold mosfets must be used. with v gate ~10 v, logic-level threshold mosfets (v gs(th) < 2.5 v) are recommended. the maximum output current (i o ) determines the r ds(on) requirement for the low-side (synchronous) mosfets. with the adp3189, currents are balanced between phases, thus the current in each low-side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and average total output current (i o ): () () sfds sf r sf o sf r n in n i dp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ?= 2 2 12 1 1 (20) knowing the maximum output current being designed for and the maximum allowed power dissipation, the user can find the required r ds(on) for the mosfet. for d-pak mosfets up to an ambient temperature of 50c, a safe limit for p sf is 1 w to 1.5 w at 120c junction temperature. thus, for this example (119 a maximum), r ds(sf) (per mosfet) < 7.5 m. this r ds(sf) is also at a junction temperature of about 120c, so be certain to account for this when making this selection. this example uses two lower-side mosfets at 4.8 m, each at 120 c. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous mosfets when the switch node goes high. also, the time to switch the synchronous mosfets off should not exceed the nonoverlap dead time of the mosfet driver (40 ns typical for the adp3120). the output impedance of the driver is approximately 2 , and the typical mosfet input gate resistances are about 1 to 2 , so a total gate capacitance of less than 6000 pf should be adhered to. since there are two mosfets in parallel, the input capacitance for each synchronous mosfet should be limited to 3000 pf. the high-side (main) mosfet has to be able to handle two main power dissipation components: conduction and switching losses. the switching loss is related to the amount of time it takes for the main mosfet to turn on and off, and to the current and voltage that are being switched. basing the switching speed on the rise and fall time of the gate driver impedance and mosfet input capacitance, the following expression provides an approximate value for the switching loss per main mosfet, where n mf is the total number of main mosfets: () iss mf g m f occ sw mfs c n n r n i v f p = 2 (21) where r g is the total gate resistance (2 for the adp3120 and about 1 for typical high speed switching mosfets, making r g = 3 ), and c iss is the input capacitance of the main mosfet. adding more main mosfets ( n mf ) does not help the switching loss per mosfet, since the additional gate capacitance slows switching. use lower gate capacitance devices to reduce switching loss. the conduction loss of the main mosfet is given by the following, where r ds(mf) is the on resistance of the mosfet: () () mfds mf r mf mfc r n in n dp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 2 2 o 12 1 i (22) typically, for main mosfets, the highest speed (low c iss ) device is preferred, but these usually have higher on resistance. select a device that meets the total power dissipation (about 1.5 w for a single d-pak) when combining the switching and conduction losses.
adp3189 rev. 0 | page 28 of 36 for this example, an ntd40n03l was selected as the main mosfet (eight total; n mf = 8), with c iss = 584 pf (max) and r ds(mf) = 19 m (max at t j = 120c), and an ntd110n02l was selected as the synchronous mosfet (eight total; n sf = 8), with c iss = 2710 pf (max) and r ds(sf) = 4.8 m (max at t j = 120c). the synchronous mosfet c iss is less than 3000 pf, satisfying this requirement. solving for the power dissipation per mosfet at io = 119 a and ir = 11 a yields 958 mw for each synchronous mosfet and 872 mw for each main mosfet. the guideline is to limit the mosfet power dissipation to 1 w. the values calculated in equation 21 and equation 22 comply with this guideline. finally, consider the power dissipation in the driver for each phase. this is best expressed as q g for the mosfets and is given by the following equation, where q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet. () cc cc gsf sf gmf mf sw drv viqnqn n f p ? ? ? ? ? ? ? ? ++ = 2 (23) also shown is the drivers standby dissipation factor (i cc v cc ). for the adp3120, the maximum dissipation should be less than 400 mw. in this example, with i cc = 7 ma, q gmf = 5.8 nc, and q gsf = 48 nc, one finds 297 mw in each driver, which is below the 400 mw dissipation limit. see the adp3120 data sheet for more details. ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. the following expression is used for determining the optimum value: k 356 pf5m2.453 nh3200.2 3 = = = r r ds d r r r cra la r (24) where a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low-side mosfet on resistance. c r is the internal ramp capacitor value. the internal ramp voltage magnitude can be calculated by using ( ) () v m439 khz330pf5k357 v1.30.10810.2 1 = ? = ? = r sw rr vid r r v fcr vda v (25) the size of the internal ramp can be made larger or smaller. if it is made larger, stability and noise rejection improves, but transient degrades. likewise, if the ramp is made smaller, transient response improves at the sacrifice of noise rejection and stability. the factor of 3 in the denominator of equation 24 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. comp pin ramp a ramp signal on the comp pin is due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input: () ? ? ? ? ? ? ? ? ? ? = o x sw r rt rcfn dn v v 12 1 (26) in this example, the overall ramp signal is 0.46 v. however, if the ramp size is smaller than 0.5 v, increase the ramp size to be at least 0.5 v by decreasing the ramp resistor for noise immunity. as there is only 0.46 v initially, a ramp resistor value of 332 k is chosen for this example, yielding an overall ramp of 0.51 v.
adp3189 rev. 0 | page 29 of 36 current limit setpoint feedback loop comp ensation design to select the current limit setpoint, first find the resistor value for r lim . the current limit threshold for the adp3189 is set with a 1.7 v source (v lim ) across r lim with a gain of 10 mv/a (a lim ). r lim can be found using csa lim lim lim lim ri va r = (27) optimized compensation of the adp3189 allows the best possible response of the regulators output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resis- tance (r o ). with the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. this ensures the optimal positioning and allows the minimization of the output decoupling. for values of r lim greater than 500 k, the current limit may be lower than expected, so some adjustment of r lim is needed. here, i lim is the peak average current limit for the supply output. in this example, choosing a peak current limit of 170 a for i lim , results in r lim = 100 k, and 100 k is chosen as the nearest 1% value. the per-phase initial duty cycle limit and peak current during a load step are determined by () rt bias max comp max v v v dd ? = (28) with the multimode feedback structure of the adp3189, the feedback compensation must be set to make the converters output impedance, working in parallel with the output decoup- ling, to meet this goal. several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for. ( ) l vv f d i vid in sw max phmax ? ? (29) a type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. equation 31 to equation 35 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning the adp3189 section). for the adp3189, the maximum comp voltage (v comp(max) ) is 4.0 v and the comp pin bias voltage (v bias ) is 1.1 v. in this example, the maximum duty cycle is 0.61 and the peak current is 62 a. first, compute the time constants for all the poles and zeros in the system, using equation 31 to equation 35 on the next page. the limit of the peak per-phase current described earlier during the secondary current limit is determined by () () maxds d bias clamped comp phlim ra v v i ? ? (30) for the adp3189, the current balancing amplifier gain (a d ) is 5, and the clamped comp pin voltage is 2 v. using an r ds(max) of 2.8 m (low-side on resistance at 150c) results in a per-phase peak current limit of 64 a. this current level can be reached only with an absolute short at the output, and the current limit latch-off function shuts down the regulator before overheating can occur.
adp3189 rev. 0 | page 30 of 36 the first step is to compute the time constants for all of the poles and zeros in the system: ( ) vid o x rt vid rt l ds d o e vrcn vdnl v vr rarnr ? + ++= 12 ( ) m9.22 v1.3m1mf6.54 v510.0.4321nh3202 v1.3 v510.m1.4 m2.45m14 = ? + ++= e r (31) () () s00.3 m0.6 m0.5m1 m1 ph024 m0.5m1mf6.5 ' ' = ? +?= ? +?= x o o x o x a r rr r l rrct (32) ( ) ( ) ns065mf6.5m1m0.5m0.6 ' = ?+=?+= x o xb crrrt (33) s17.5 m9.22v1.3 khz3302 m2.45 nh320v510. 2 = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? = e vid sw ds d rt c rv f ra lv t (34) () ( ) () ns833 m1f180m0.5m1mf6.5 m1f180mf6.5 ' 2 2 = +? = +? = o z o x o z x d rcrrc rcc t (35) where, for the adp3189, r ' is the pcb resistance from the bulk capacitors to the ceramics and where r ds is the total low-side mosfet on resistance per phase. in this example, a d is 5, v rt equals 0.51 v, r ' is approximately 0.5 m (assuming a 4-layer, 1 ounce mother- board), and l x is 240 ph for the ten al-poly capacitors. the compensation values can then be solved using pf524 k001.m9.22 s00.3m14 = = = be ao a rr trn c (36) k87.9 pf524 s17.5 === a c a c t r (37) pf560 k001. ns065 === b b b r t c (38) pf2.34 k87.9 ns833 === a d fb r t c (39) these are the starting values prior to tuning the design to account for layout and other parasitic effects (see the tuning the adp3189 section). the final values selected after tuning are c a = 560 pf r a = 10.0 k c b = 560 pf c fb = 27 pf
adp3189 rev. 0 | page 31 of 36 figure 14 and figure 15 show the typical transient response using these compensation values. 05626-014 figure 14. typical transient response for design example load step 05626-015 figure 15. typical transient response for design example load release c in selection and input current di/dt reduction in continuous inductor current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude of one-nth the maximum output current. to prevent large voltage transients, a low esr input capacitor, sized for the maximum rms current, must be used. the maximum rms capacitor current is given by a14.71 0.1084 1 a191108.0 1 dn 1 =? = ? = crms o crms i idi (40) the capacitor manufacturers ripple current ratings are often based on only 2,000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may be placed in parallel to meet size or height requirements in the design. in this example, the input capacitor bank is formed by two 2,700 f, 16 v aluminum electrolytic capacitors, and eight 4.7 f ceramic capacitors. to reduce the input current di/dt to a level below the recom- mended maximum of 0.1 a/s, an additional small inductor (l > 370 nh at 18 a) should be inserted between the converter and the supply bus. this inductor also acts as a filter between the converter and the primary power source. thermal monitor design a thermistor is used on the ttsense input of the adp3189 for monitoring the temperature of the vr. a constant current of 120 a is sourced out of this pin and run through a thermis- tor network such as that shown in figure 16 . ttsense vrhot vrfan 9 10 8 adp3189 optional temperature adjust resistor 0.1 place thermistor near closest phase r ttsense 05626-016 figure 16. vr thermal monitor circuit a voltage is generated from this current through the thermistor and sensed inside the ic. when the voltage reaches 1.11 v, the vrfan output gets set. when the voltage reaches 0.81 v, the vrhot gets set. this corresponds to r ttsense values of 9.25 k for vrfan and 6.75 k. these values correspond to a thermistor temperature of ~100c and ~110c when using the same type of 100 k ntc thermistor used in the current sense amplifier. an additional fixed resistor in parallel with the thermistor provides tuning the trip point temperatures to match the hot- test temperature in the vr, when the thermistor itself is directly sensing a proportionately lower temperature. setting this resistor value is best accomplished with a variable resistor during thermal validation, and then fixing this value for the final design. additionally, a 0.1 f should be used for filtering noise.
adp3189 rev. 0 | page 32 of 36 tuning the adp3189 1. build a circuit based on the compensation values computed from the design spreadsheet. 2. hook up the dc load to circuit, turn it on, and verify its operation. also, check for jitter at no load and full load. dc loadline setting 3. measure the output voltage at no load (v nl ). verify that it is within tolerance. 4. measure the output voltage at full load cold (v flcold ). let the board sit for ~10 minutes at full load, and then measure the output (v flhot ). if there is a change of more than a few millivolts, adjust r cs1 and r cs2 using equation 41 and equation 43. () () flhot nl flcold nl oldcs2 newcs2 vv v v r r ? ? = (41) 5. repeat step 4 until the cold and hot voltage measurements remain the same. 6. measure the output voltage from no load to full load using 5 a steps. compute the loadline slope for each change, and then average to get overall loadline slope (r omeas ). 7. if r omeas is off from r o by more than 0.05 m, use the following to adjust the r ph values: () () o omeas oldph newph r r r r = (42) 8. repeat step 6 and step 7 to check the loadline, and repeat adjustments if necessary. 9. once dc loadline adjustment is complete, do not change r ph , r cs1 , r cs2 , or r th for the remainder of the procedure. 10. measure the output ripple at no load and full load with a scope, and make sure it is within specifications. () () ( ) () ( ) () () () () ( ) () () c25 c25 c25 c25 1 1 ? ? ? + + = th th oldcs1 newcs2 oldcs1 th oldcs1 th oldcs1 newcs1 r rr rr r r r r r (43)
adp3189 rev. 0 | page 33 of 36 ac loadline setting 11. remove the dc load from the circuit and hook up the dynamic load. 12. hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. set the dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 14. measure the output waveform (use dc offset on scope to see the waveform). try to use a vertical scale of 100 mv/div or finer. this waveform should look similar to figure 17 . v acdrp v dcdrp 05626-017 figure 17. ac loadline waveform 15. use the horizontal cursors to measure v acdrp and v dcdrp as shown. do not measure the undershoot or overshoot that happens immediately after this step. 16. if v acdrp and v dcdrp are different by more than a few millivolts, use equation 44 to adjust c cs . yo u m a y n e e d t o parallel different values to get the right one since there are limited standard capacitor values available. (it is a good idea to have locations for two capacitors in the layout for this.) () () dcdrp acdrp oldcs newcs v v c c = (44) 17. repeat step 11 to step 13 and repeat the adjustments if necessary. once complete, do not change c cs for the remainder of the procedure. set the dynamic load step to maximum step size (do not use a step size larger than needed) and verify that the output waveform is square, which means that v acdrp and v dcdrp are equal. initial transient setting 18. with the dynamic load still set at the maximum step size, expand the scope time scale to see 2 s/div to 5 s/div. the waveform can have two overshoots and one minor undershoot (see figure 18 ). here, v droop is the final desired value. v droop v tran1 v tran2 05626-018 figure 18. transient setting waveform 19. if both overshoots are larger than desired, try making the adjustments described later in this step. if these adjustments do not change the response, you are limited by the output decoupling. check the output response each time you make a change, and check the switching nodes to make ensure that the response is still stable. ? make the ramp resistor larger by 25% (r ramp ). ? for v tran1 , increase c b or increase the switching frequency. ? for v tran2 , increase r a and decrease c a by 25%. 20. for load release (see figure 19 ), if v tranrel is larger than the allowed overshoot, there is not enough output capacitance. either more capacitance is needed, or the inductor values need to be made smaller. (when changing inductors, start the design again using a spreadsheet and this tuning procedure.) v droop v tranrel 05626-019 figure 19. transient setting waveform
adp3189 rev. 0 | page 34 of 36 since the adp3189 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. therefore, the user does not have to add headroom for ripple, allowing load release vtranrel to be larger than vtran1, by the amount of ripple, and still meet specifications. if v tran1 and v tranrel are less than the desired final droop, this implies that capacitors can be removed. when removing capaci- tors, check the output ripple voltage as well to make sure it is still within specifications. layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for good results, a pcb with at least four layers is recommended. this should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. whenever high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the adp3189) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. an analog ground plane should be used around and under the adp3189 as a reference for the components associated with the controller. this plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. the components around the adp3189 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb pin and cssum pin. the output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. if the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop, described in the power circuitry recommendations section. power circuitry recommendations the switching power path should be routed on the pcb to encompass the shortest-possible length in order to minimize radiated switching noise energy (that is, emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system and noise- related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. whenever a power dissipating component, for example, a power mosfet, is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are improved current rating through the vias and improved thermal perform- ance from vias extended to the opposite side of the pcb, where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heatsink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improve thermal performance, use the largest possible pad area. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. signal circuitry recommendations the output voltage is sensed and regulated between the fb pin and the fbrtn pin, which connect to the signal ground at the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be small. thus, the fb trace and fbrtn trace should be routed adjacent to each other on top of the power ground plane back to the controller. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be connected to the output voltage at the nearest inductor to the controller.
adp3189 rev. 0 | page 35 of 36 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bcs sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vjjd-2 figure 20. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity adp3189jcpz-rl 1 0c to 85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40 2500 1 z = pb-free part.
adp3189 rev. 0 | page 36 of 36 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05626C0C7/05(0)

▲Up To Search▲

Price & Availability of ADP3189JCPZ-RLZ

	To Download ADP3189JCPZ-RLZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .